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general description the max1316?ax1318/max1320?ax1322/max1324 max1326 14-bit, analog-to-digital converters (adcs) offer two, four, or eight independent input channels. independent track/hold (t/h) circuitry provides simultane- ous sampling for each channel. the max1316/ max1317/max1318 have a 0 to +5v input range with ?.0v fault-tolerant inputs. the max1320/max1321/ max1322 have a ?v input range with ?6.5v fault-toler- ant inputs. the max1324/max1325/max1326 have a ?0v input range with ?6.5v fault-tolerant inputs. these adcs convert two channels in 2s, and up to eight chan- nels in 3.8?, and have an 8-channel throughput of 250ksps per channel. other features include a 10mhz t/h input bandwidth, internal clock, internal (+2.5v) or external (+2.0v to +3.0v) reference, and power- saving modes. a 16.6mhz, 14-bit, bidirectional, parallel interface pro- vides the conversion results and accepts digital config- uration inputs. these devices operate from a +4.75v to +5.25v analog supply and a separate +2.7v to +5.25v digital supply, and consume less than 50ma total supply current. these devices come in a 48-pin tqfp package and oper- ate over the extended -40? to +85? temperature range. applications multiphase motor control power-grid synchronization power-factor monitoring and correction vibration and waveform analysis features ? 8-/4-/2-channel, 14-bit adcs ?.5 lsb inl, ? lsb dnl, no missing codes 90dbc sfdr, -86dbc thd, 76.5db sinad, 77db snr at 100khz input ? on-chip t/h circuit for each channel 10ns aperture delay 50ps channel-to-channel t/h matching ? fast conversion time one channel in 1.6? two channels in 1.9? four channels in 2.5? eight channels in 3.7? ? high throughput 526ksps/ch for one channel 455ksps/ch for two channels 357ksps/ch for four channels 250ksps/ch for eight channels ? flexible input ranges 0 to +5v (max1316/max1317/max1318) ?v (max1320/max1321/max1322) ?0v (max1324/max1325/max1326) ? no calibration needed ? 14-bit, high-speed, parallel interface ? internal or external clock ? +2.5v internal reference or +2.0v to +3.0v external reference ? +5v analog supply, +3v to +5v digital supply 46ma analog supply current (typ) 1.6ma digital supply current (max) shutdown and power-saving modes ? 48-pin tqfp package (7mm ? 7mm footprint) max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ________________________________________________________________ maxim integrated products 1 ordering information selector guide 19-3157; rev 2; 8/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations and typical operating circuits appear at end of data sheet. * future product?ontact factory for availability. part temp range pin-package max1316 ecm -40 c to +85 c 48 tqfp max1317 ecm -40 c to +85 c 48 tqfp max1318 ecm -40 c to +85 c 48 tqfp max1320 ecm -40 c to +85 c 48 tqfp max1321 ecm -40 c to +85 c 48 tqfp max1322 ecm -40 c to +85 c 48 tqfp max1324 ecm -40 c to +85 c 48 tqfp max1325 ecm -40 c to +85 c 48 tqfp max1326 ecm -40 c to +85 c 48 tqfp part input range (v) channel count max1316ecm 0 to +5 8 max1317ecm 0 to +5 4 max1318ecm 0 to +5 2 MAX1320ECM ? 8 max1321ecm ? 4 max1322ecm ? 2 max1324ecm ?0 8 max1325ecm ?0 4 max1326ecm ?0 2
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = +5v, dv dd = +3v, agnd = dgnd = 0v, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1f, c com = 2.2? || 0.1f, c msv = 2.2? || 0.1f (unipolar devices, max1316/ max1317/max1318), msv = agnd (bipolar devices, max1320/max1321/max1322/max1324/max1325/max1326), f clk = 10mhz, 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = t min to t max , unless otherwise noted. typical val- ues are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v ch0?h7, i.c. to agnd (max1316/max1317/max1318)...?.0v ch0?h7, i.c. to agnd (max1320/max1321/max1322).?6.5v ch0?h7, i.c. to agnd (max1324/max1325/max1326).?6.5v intclk/ extclk to agnd .......................-0.3v to (av dd + 0.3v) eoc , eolc , wr , rd , cs to dgnd .........-0.3v to (dv dd + 0.3v) convst, clk, shdn, allon to dgnd..................................-0.3v to (dv dd + 0.3v) msv, ref ms , ref to agnd.....................-0.3v to (av dd + 0.3v) ref+, com, ref- to agnd.....................-0.3v to (av dd + 0.3v) d0?13 to dgnd ....................................-0.3v to (dv dd + 0.3v) maximum current into any pin except av dd , dv dd , agnd, dgnd...............................................................?0ma continuous power dissipation tqfp (derate 22.7mw/? above +70?) ...................1818mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units static performance (note 1) resolution n 14 bits integral nonlinearity inl (note 2) 0.8 2.0 lsb differential nonlinearity dnl no missing codes (note 2) 0.5 1 lsb unipolar devices 40 offset error bipolar devices 40 lsb unipolar devices -4 offset drift bipolar devices -4 ppm/ c unipolar devices between all channels 35 80 channel offset matching bipolar devices between all channels 25 60 lsb gain error (note 3) 8 40 lsb channel gain-error matching between all channels 25 lsb gain temperature coefficient 3 ppm/ c dynamic performance (at f in = 100khz, -0.4db fs) unipolar 74.5 76 signal-to-noise ratio snr bipolar 75 76.5 db unipolar 74.5 76 signal-to-noise and distortion ratio sinad bipolar 75 76.5 db spurious-free dynamic range sfdr 83 93 dbc total harmonic distortion thd -90 -83 dbc channel-to-channel isolation 83 db analog inputs (ch0?h7) max1316/max1317/max1318 0 +5 max1320/max1321/max1322 -5 +5 input voltage range max1324/max1325/max1326 -10 +10 v
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0v, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1f, c com = 2.2? || 0.1f, c msv = 2.2? || 0.1f (unipolar devices, max1316/ max1317/max1318), msv = agnd (bipolar devices, max1320/max1321/max1322/max1324/max1325/max1326), f clk = 10mhz, 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = t min to t max , unless otherwise noted. typical val- ues are at t a = +25?.) parameter symbol conditions min typ max units v in = +5v 0.54 0.72 max1316/max1317/max1318 v in = 0v -0.157 -0.12 v in = +5v 0.29 0.39 max1320/max1321/max1322 v in = -5v -1.16 -0.87 v in = +10v 0.56 0.74 input current (note 4) max1324/max1325/max1326 v in = -10v -1.13 -0.85 ma max1316/max1317/max1318 7.58 max1320/max1321/max1322 8.66 input resistance (note 4) max1324/max1325/max1326 14.26 ? input capacitance 15 pf track/hold one channel 526 two channels 455 four channels 357 external-clock throughput rate (note 5) eight channels 250 ksps one channel (intclk/ extclk = av dd ) 526 two channels (intclk/ extclk = av dd ) 455 four channels (intclk/ extclk = av dd ) 357 internal-clock throughput rate (note 5) eight channels (intclk/ extclk = av dd ) 250 ksps small-signal bandwidth 10 mhz full-power bandwidth 10 mhz aperture delay 16 ns aperture jitter 50 ps rms aperture-delay matching 100 ps internal reference ref ms voltage v refms 2.475 2.500 2.525 v ref voltage v ref 2.475 2.500 2.525 v ref temperature coefficient 30 ppm/ c external reference (ref ms and ref externally driven) input current -250 +250 ? ref ms input voltage range v refms unipolar devices 2.0 2.5 3.0 v ref voltage input range v ref 2.0 2.5 3.0 v ref input capacitance 15 pf ref ms input capacitance 15 pf digital inputs (d0?7, rd , wr , cs , clk, shdn, allon, convst) input-voltage high v ih 0.7 x dv dd v
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0v, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1f, c com = 2.2? || 0.1f, c msv = 2.2? || 0.1f (unipolar devices, max1316/ max1317/max1318), msv = agnd (bipolar devices, max1320/max1321/max1322/max1324/max1325/max1326), f clk = 10mhz, 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = t min to t max , unless otherwise noted. typical val- ues are at t a = +25?.) parameter symbol conditions min typ max units input-voltage low v il 0.3 x dv dd v input hysteresis 15 mv input capacitance c in 15 pf input current i in v in = 0v or dv dd 1a clock-select input (intclk/ extclk ) input-voltage high 0.7 x av dd v input-voltage low 0.3 x av dd v digital outputs (d0?13, eoc , eolc ) output-voltage high v oh i source = 0.8ma dv dd - 0.6 v output-voltage low v ol i sink = 1.6ma 0.4 v tri-state leakage current rd v ih or cs v ih 0.06 1a tri-state output capacitance rd v ih or cs v ih 15 pf power supplies analog-supply voltage av dd 4.75 5.25 v digital-supply voltage dv dd 2.70 5.25 v max1316/max1317/max1318, all channels selected 46 51 max1320/max1321/max1322, all channels selected 46 51 analog-supply current i avdd max1324/max1325/max1326, all channels selected 46 51 ma max1316/max1317/max1318, all channels selected 1 1.6 max1320/max1321/max1322, all channels selected 1 1.6 digital-supply current (note 6) i dvdd c load = 100pf max1324/max1325/max1326, all channels selected 1 1.6 ma i avdd v shdn = dv dd , v ch = float 10 shutdown current (note 7) i dvdd v rd = v wr = dv dd , v shdn = dv dd 0.1 2 ? power-supply rejection ratio psrr av dd = +4.75v to +5.75v (note 8) 50 db
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges _______________________________________________________________________________________ 5 note 1: for the max1316/max1317/max1318, v in = 0 to +5v. for the max1320/max1321/max1322, v in = -5v to +5v. for the max1324/max1325/max1326, v in = -10v to +10v. note 2: all channel performance is guaranteed by correlation to a single channel test. note 3: offset nulled. note 4: the analog input resistance is terminated to an internal bias point. calculate the analog input current using: for v ch within the input voltage range. note 5: throughput rate is given per channel. throughput rate is a function of clock frequency (f clk = 10mhz). see the data throughput section for more information. note 6: all analog inputs are driven with an fs 100khz sine wave. i vv r ch ch bias ch _ _ _ = ? timing characteristics (figures 3, 4, 5, 6 and 7) (tables 1, 3) parameter symbol conditions min typ max units internal clock 1.6 1.8 ? time-to-first-conversion result t conv external clock, figure 6 16 clock cycles internal clock 0.3 0.36 ? time-to-next-conversion result t next external clock, figure 6 3 clock cycles convst pulse-width low (acquisition time) t acq (note 9) 0.16 100 ? cs pulse width t 2 30 ns rd pulse-width low t 3 30 ns rd pulse-width high t 4 30 ns wr pulse-width low t 5 30 ns cs to wr t 6 (note 10) ns wr to cs t 7 (note 10) ns cs to rd t 8 (note 10) ns rd to cs t 9 (note 10) ns data-access time ( rd low to valid data) t 10 30 ns bus-relinquish time ( rd high) t 11 30 ns internal clock 80 ns eoc pulse width t 12 external clock, figure 6 1 clock cycles input-data setup time t 14 10 ns input-data hold time t 15 10 ns external-clock period t 16 0.08 10.00 ? external-clock high period t 17 logic sensitive to rising edges 20 ns external-clock low period t 18 logic sensitive to rising edges 20 ns external-clock frequency (note 11) 0.1 12.5 mhz internal-clock frequency 10 mhz convst high to clk edge t 19 20 (note 12) ns eoc low to rd t 20 0ns
integral nonlinearity vs. digital output code max1316 toc01 digital output code inl (lsb) 12288 8192 4096 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 16384 differential nonlinearity vs. digital output code max1316 toc02 digital output code dnl (lsb) 12288 8192 4096 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 16384 analog supply current vs. supply voltage max1316 toc03 supply voltage (v) supply current (ma) 5.12 5.00 4.87 35 40 45 50 30 4.75 5.25 f sample = 250ksps all 8 channels driven with full- scale sine waves analog supply current vs. temperature max1316 toc04 temperature ( c) supply current (ma) 60 35 10 -15 35 40 45 50 30 -40 85 f sample = 250ksps all 8 channels driven with full- scale sine waves shutdown current vs. supply voltage max1316 toc05 supply voltage (v) shutdown current ( a) 4.5 3.5 0.2 0.4 0.6 0.8 0 2.5 5.5 analog shutdown current digital shutdown current shutdown current vs. temperature max1316 toc06 temperature ( c) shutdown current ( a) 60 35 10 -15 0.2 0.4 0.6 0.8 0 -40 85 analog shutdown current digital shutdown current max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 6 _______________________________________________________________________________________ timing characteristics (figures 3, 4, 5, 6 and 7) (tables 1, 3) (continued) note 7: shutdown current is measured with analog input floating. the large amplitude of the maximum shutdown current specifi- cation is due to automatic test equipment limitations. note 8: defined as the change in positive full scale caused by ?% variation in the nominal supply voltage. note 9: convst must remain low for at least the acquisition period. the maximum acquisition time is limited by internal capacitor droop. note 10: cs -to- wr and cs -to- rd pins are internally and together. setup and hold times do not apply. note 11: minimum clock frequency is limited only by the internal t/h droop rate. limit the time between the falling edge of convst to the falling edge of eolc to a maximum of 0.25ms. note 12: to avoid t/h droop degrading the sampled analog input signals, the first clock pulse should occur within 10? of the ris- ing edge of convst, and have a minimum clock frequency of 100khz. typical operating characteristics (av dd = +5v, dv dd = +3v, agnd = dgnd = 0v, v ref = v refms = +2.5v (external reference), see the typical operating circuits sec- tion, f clk = 10mhz, 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = +25?, unless otherwise noted.)
typical operating characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0v, v ref = v refms = +2.5v (external reference), see the typical operating circuits sec- tion, f clk = 10mhz, 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = +25?, unless otherwise noted.) internal reference voltage vs. analog supply voltage max1316 toc07 av dd (v) v ref (v) 5.2 5.1 4.8 4.9 5.0 2.4997 2.4998 2.4999 2.5000 2.5001 2.5002 2.5003 2.5004 2.4996 4.7 5.3 internal reference voltage vs. temperature max1316 toc08 temperature ( c) v ref (v) 60 35 -15 10 2.497 2.498 2.499 2.500 2.501 2.502 2.503 2.504 2.496 -40 85 offset error vs. supply voltage max1316 toc09 av dd (v) offset error (lsb) 5.15 5.05 4.95 4.85 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 -2.0 4.75 5.25 normalized at t a = +25 c max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges _______________________________________________________________________________________ 7 offset error vs. temperature max1316 toc10 temperature ( c) offset error (%fsr) 60 35 -15 10 -0.03 -0.02 -0.01 0 0.02 0.01 0.03 0.04 -0.04 -40 85 normalized at t a = +25 c gain error vs. supply voltage max1316 toc11 av dd (v) gain error (lsb) 5.15 5.05 4.95 4.85 10 11 12 13 14 15 16 9 4.75 5.25 gain error vs. temperature max1316 toc12 temperature ( c) gain error (%fsr) 60 35 -15 10 0.02 0.03 0.04 0.05 0.07 0.06 0.08 0.09 0.01 -40 85
typical operating characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0v, v ref = v refms = +2.5v (external reference), see the typical operating circuits sec- tion, f clk = 10mhz, 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = +25?, unless otherwise noted.) fft max1316 toc13 frequency (mhz) amplitude (db) 0.20 0.15 0.10 0.05 -120 -100 -80 -60 -40 -20 0 -140 0 0.25 f analog_in = 103khz f sample = 490khz f clk = 10mhz sinad = 76.7db snr = 77.0db thd = -88.3db sfdr = 91.0db signal-to-noise ratio vs. clock frequency max1316 toc14 f clk (mhz) snr (db) 18 16 14 12 10 71 72 73 74 75 76 77 78 79 80 70 820 f in = 100khz signal-to-noise plus distortion vs. clock frequency max1316 toc15 f clk (mhz) sinad (db) 18 16 14 12 10 71 72 73 74 75 76 77 78 79 80 70 820 f in = 100khz effective number of bits vs. clock frequency max1316 toc16 f clk (mhz) enob (bits) 18 16 14 12 10 820 11.0 11.5 12.0 12.5 13.0 13.5 10.5 f in = 100khz total harmonic distortion vs. clock frequency max1316 toc17 f clk (mhz) thd (db) 18 16 14 12 10 820 -95 -90 -85 -80 -75 -70 -100 spurious-free dynamic range vs. clock frequency max1316 toc17b f clk (mhz) sfdr (db) 18 16 14 12 10 820 65 70 75 80 85 90 95 100 60 max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 8 _______________________________________________________________________________________
output histogram (dc input) max1316 toc20 digital output code counts 8217 8216 8214 8215 8211 8212 8213 8210 500 1000 1500 2000 2500 3000 3500 4000 4500 0 010 13 8209 2306 1562 154 341 3815 conversion time vs. temperature max1316 toc19 temperature ( c) conversion time ( s) 60 35 10 -15 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 -40 85 t next t conv internal clock conversion time vs. analog supply voltage max1316 toc18 analog supply voltage (v) conversion time ( s) 5.125 5.000 4.875 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 4.750 5.250 t next t conv internal clock typical operating characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0v, v ref = v refms = +2.5v (external reference), see the typical operating circuits sec- tion, f clk = 10mhz, 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = +25?, unless otherwise noted.) max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges _______________________________________________________________________________________ 9 pin description pin max1316 max1320 max1324 max1317 max1321 max1325 max1318 max1322 max1326 name function 1, 15, 17 1, 15, 17 1, 15, 17 av dd analog supply input. av dd is the power input for the analog section of the converter. apply 4.75v to 5.25v to av dd . bypass av dd to agnd (pin 14 to pin 15, pin 16 to pin 17, pin 1 to pin 2) with a 0.1? capacitor at each av dd input. 2, 3, 14, 16, 23 2, 3, 14, 16, 23 2, 3, 14, 16, 23 agnd analog ground. agnd is the power return for av dd . connect all agnds together. 4 4 4 ch0 channel 0 analog input 5 5 5 ch1 channel 1 analog input 666msv midscale voltage bypass. for the max1316/max1317/max1318, connect a 2.2? and a 0.1? capacitor from msv to agnd. for the max1320/max1321/max1322/max1324/max1325/max1326, connect msv directly to agnd. 7 7 ch2 channel 2 analog input 8 8 ch3 channel 3 analog input 9 ch4 channel 4 analog input
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 10 ______________________________________________________________________________________ pin description (continued) pin max1316 max1320 max1324 max1317 max1321 max1325 max1318 max1322 max1326 name function 10 ch5 channel 5 analog input 11 ch6 channel 6 analog input 12 ch7 channel 7 analog input 13 13 13 intclk/ extclk clock-mode select input. use intclk/ extclk to select the internal or external conversion clock. connect intclk/ extclk to av dd to select the internal clock. connect intclk/ extclk to agnd to use an external clock connected to clk. 18 18 18 ref ms midscale reference bypass or input. ref ms is the bypass point for an internally generated reference voltage. for the max1316/ max1317/max1318, connect a 0.1? capacitor from ref ms to agnd. for the max1320/max1321/max1322/max1324/ max1325/max1326, connect ref ms directly to ref and bypass with a 0.1? capacitor from ref ms to agnd. 19 19 19 ref adc reference bypass or input. ref is the bypass point for an internally generated reference voltage. bypass ref with a 0.01? capacitor to agnd. ref can be driven externally by a precision external voltage reference. 20 20 20 ref+ positive reference bypass. ref+ is the bypass point for an internally generated reference voltage. bypass ref+ with a 0.1? capacitor to agnd. also bypass ref+ to ref- with a 2.2? and a 0.1? capacitor. 21 21 21 com reference common bypass. com is the bypass point for an internally generated reference voltage. bypass com to agnd with a 2.2? and a 0.1? capacitor. 22 22 22 ref- negative reference bypass. ref- is the bypass point for an internally generated reference voltage. bypass ref- with a 0.1? capacitor to agnd. also bypass ref- to ref+ with a 2.2? and a 0.1? capacitor. 24 24 24 d0 digital i/o bit 0 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 25 25 25 d1 digital i/o bit 1 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 26 26 26 d2 digital i/o bit 2 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1.
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 11 pin description (continued) pin max1316 max1320 max1324 max1317 max1321 max1325 max1318 max1322 max1326 name function 27 27 27 d3 digital i/o bit 3 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 28 28 28 d4 digital i/o bit 4 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 29 29 29 d5 digital i/o bit 5 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 30 30 30 d6 digital i/o bit 6 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 31 31 31 d7 digital i/o bit 7 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 32 32 32 d8 digital out bit 8 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 33 33 33 d9 digital out bit 9 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 34 34 34 d10 digital out bit 10 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 35 35 35 d11 digital out bit 11 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 36 36 36 d12 digital out bit 12 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 37 37 37 d13 digital out bit 13 of 14-bit parallel data bus. high impedance when rd = 1 or cs = 1. 38 38 38 dv dd digital-supply input. apply +2.7v to +5.25v to dv dd . bypass dv dd to dgnd with a 0.1? capacitor. 39 39 39 dgnd digital-supply gnd. dgnd is the power return for dv dd . connect dgnd to agnd at only one point (see the layout, grounding, and bypassing section). 40 40 40 eoc end-of-conversion output. eoc goes low to indicate the end of a conversion. eoc returns high after one clock period.
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 12 ______________________________________________________________________________________ pin description (continued) pin max1316 max1320 max1324 max1317 max1321 max1325 max1318 max1322 max1326 name function 41 41 41 eolc end-of-last-conversion output. eolc goes low to indicate the end of the last conversion. eolc returns high when convst goes low for the next conversion sequence. 42 42 42 rd read input. when rd and cs go low, the device initiates a read command of the parallel data buses, d0?13. d0?13 are high impedance while either rd or cs is high. 43 43 43 wr write input. the write command initiates when wr and cs go low. a write command loads the configuration byte on d0?7. 44 44 44 cs chip-select input. pulling cs low activates the digital interface. d0?13 are high impedance while either cs or rd is high. 45 45 45 convst convert-start input. driving convst high places the device in hold mode and initiates the conversion process. the analog inputs are sampled on the rising edge of convst. when convst is low, the analog inputs are tracked. 46 46 46 clk external-clock input. clk accepts an external-clock signal up to 15mhz. connect clk to dgnd for internally clocked conversions. to select external-clock mode, set intclk/ extclk = 0. 47 47 47 shdn shutdown input. set shdn = 0 for normal operation. set shdn = 1 for shutdown mode. 48 48 48 allon enable-all-channels input. drive allon high to enable all input channels. when allon is low, only input channels selected as active are powered. select channels as active using the configuration register. 9?2 7?2 i.c. internally connected. connect i.c. to agnd. for factory use only.
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 13 detailed description the max1316?ax1318/max1320?ax1322/max1324- max1326 are 14-bit adcs. they offer two, four, or eight (independently selectable) input channels, each with its own t/h circuitry. simultaneous sampling of all active channels preserves relative phase information, making these devices ideal for motor control and power monitor- ing. these devices are available with 0 to +5v, ?v, and ?0v input ranges. the 0 to +5v devices feature ?v fault-tolerant inputs. the ?v and ?0v devices feature ?6.5v fault-tolerant inputs. two channels convert in 2s; all eight channels convert in 3.8?, with a maximum 8- channel throughput of 263ksps per channel. internal or external reference and internal- or external-clock capabil- ity offer great flexibility and ease of use. a write-only con- figuration register can mask out unused channels, and a shutdown feature reduces power. a 16.6mhz, 14-bit, par- allel data bus outputs the conversion result. figure 1 shows the functional diagram of these devices. analog inputs t/h to preserve phase information across these multichan- nel devices, each input channel has a dedicated t/h amplifier. use a low-input source impedance to minimize gain- error harmonic distortion. the time required for the t/h to acquire an input signal depends on the input source impedance. if the input signal? source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. the acquisition time (t 1 ) is the maximum time the device takes to acquire the signal. use the following formula to calcu- late acquisition time: t 1 = 10 (r s + r in ) x 6pf where r in = 2.2k ? , r s = the input signal? source impedance, and t 1 is never less than 180ns. a source impedance of less than 100 ? does not significantly affect the adc? performance. figure 1. functional diagram max1316?ax1318 max1320?ax1322 max1324?ax1326 convst d13 msv dgnd av dd shdn clk ch0 interface and control 8 x 1 mux 14-bit adc ch7 d0 dv dd agnd allon ref ms ref ref+ com ref- s/h s/h 8 x 14 sram output drivers 5k ? 5k ? configuration register d7 d8 2.500v * *switch closed on unipolar devices, open on bipolar devices intclk/extclk wr cs rd eoc eolc
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 14 ______________________________________________________________________________________ to improve the input-signal bandwidth under ac condi- tions, drive the input with a wideband buffer (>50mhz) that can drive the adc? input capacitance and settle quickly. for example, the max4265 can be used for +5v unipolar devices, or the max4350 can be used for ?v bipolar inputs. the t/h aperture delay is typically 13ns. the aperture- delay mismatch between t/hs of 50ps allows the relative phase information of up to eight different inputs to be preserved. figure 2 shows a simplified equivalent input circuit, illustrating the adc? sampling architecture. input bandwidth the input tracking circuitry has a 12mhz small-signal bandwidth, making it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. input range and protection these devices provide ?0v, ?v, or 0 to +5v analog input voltage ranges. figure 2 shows the equivalent input circuit. overvoltage protection circuitry at the analog input provides ?6.5v fault protection for the bipolar input devices and ?.0v fault protection for the unipolar input devices. this fault-protection circuit limits the current going into or out of the device to less than 50ma, provid- ing an added layer of protection from momentary over- voltage or undervoltage conditions at the analog input. power-saving modes shutdown mode during shutdown, the analog and digital circuits in the device power down and the device draws less than 100? from av dd , and less than 100? from dv dd . select shutdown mode using the shdn input. set shdn high to enter shutdown mode. after coming out of shut- down, allow a 1ms wake-up time before making the first conversion. when using an external clock, apply at least 20 clock cycles with convst high before making the first conversion. when using internal-clock mode, wait at least 2? before making the first conversion. allon allon is useful when some of the analog input channels are selected (see the configuration register section). drive allon high to power up all input channel circuits, regardless of whether they are selected as active by the configuration register. drive allon low or connect to ground to power only the input channels selected as active by the configuration register, saving 2ma per channel (typ). the wake-up time for any channel turned on with the configuration register is 2? (typ) when allon is low. the wake-up time with allon high is only 0.01?. new configuration-register information does not become active until the next convst falling edge. therefore, when using software to control power states (allon = 0), pulse convst low once before applying the actual convst signal (figure 3). with an external clock, apply at least 15 clock cycles before the second convst. if using internal-clock mode, wait at least 1.5? or until the first eoc before generating the second convst. figure 2. typical input circuit ch_ r1 r2 v bias c par 1pf 5pf max1316?ax1318 max1320?ax1322 max1324?ax1326 input range (v) 0 to +5 5 10 r1 (k ? ) 3.33 6.67 13.33 r2 (k ? ) 5.00 2.86 2.35 v bias (v) 0.90 2.50 2.06 table 1. conversion times using the internal clock number of channels internal-clock conversion time 1 1.6 2 1.9 3 2.2 4 2.5 5 2.8 6 3.1 7 3.4 8 3.7
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 15 clock modes these devices provide an internal clock of 10mhz (typ). alternatively, an external clock can be used. internal clock internal-clock mode frees the microprocessor from the burden of running the adc conversion clock. for internal- clock operation, connect intclk/ extclk to av dd and connect clk to dgnd. table 1 illustrates the total con- version time using internal-clock mode. external clock for external-clock operation, connect intclk/ extclk to agnd and connect an external-clock source to clk. note that intclk/ extclk is referenced to the analog power supply, av dd . the external-clock frequency can be up to 15mhz, with a duty cycle between 30% and 70%. clock frequencies of 100khz and lower can be used, but the droop in the t/h circuits reduce linearity. selecting an input buffer most applications require an input buffer to achieve 14- bit accuracy. although slew-rate and bandwidth are important, the most critical specification is settling time. the sampling requires a relatively brief sampling inter- val of 150ns. at the beginning of the acquisition, the internal sampling capacitor array connects to ch_ (the amplifier output), causing some output disturbance. ensure the amplifier is capable of settling to at least 14- bit accuracy during this interval. use a low-noise, low- distortion, wideband amplifier (such as the max4350 or max4265), which settles quickly and is stable with the adc? capacitive load (in parallel with any bypass capacitors on the analog inputs). applications section digital interface the bidirectional, parallel, digital interface sets the 8-bit configuration register (see the configuration register section) and outputs the 14-bit conversion result. the interface includes the following control signals: chip select ( cs ), read ( rd ), write ( wr ), end of conversion ( eoc ), end of last conversion ( eolc ), convert start (convst), shutdown (shdn), all on (allon), internal- clock select (intclk / extclk ), and external-clock input (clk). figures 4, 5, 6, 7, table 4, and the timing characteristics section show the operation of the inter- face. d0?7 are bidirectional, and d8?13 are output only. all bits are high impedance when rd = 1 or cs = 1. configuration register enable channels as active by writing to the configuration register through i/o lines d0?7 (table 2). the bits in the configuration register map directly to the channels, with d0 controlling channel zero, and d7 controlling channel seven. setting any bit high activates the corresponding input channel, while resetting any bit low deactivates the corresponding channel. devices with fewer than eight channels contain some bits that have no function. figure 3. software channel wake-up timing (allon = 0) convst d0?7 clk wr eoc eolc latch t acq t acq dummy conversion start actual conversion start data-in data-in changes one or more channels from power-down to active mode 12345 1415 1 >14 cycles sample
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 16 ______________________________________________________________________________________ to write to the configuration register, pull cs and wr low, load bits d0?7 onto the parallel bus, and force wr high. the data are latched on the rising edge of wr (figure 4). it is possible to write to the configuration register at any point during the conversion sequence; however, it is not active until the next convert-start sig- nal. at power-up, write to the configuration register to select the active channels before beginning a conver- sion. shutdown does not change the configuration reg- ister. see the shutdown mode and the allon sections for information about using the configuration register for power saving. starting a conversion to start a conversion using internal-clock mode, pull convst low for at least the acquisition time (t 1 ). the t/h acquires the signal while convst is low, and con- version begins on the rising edge of convst. an end- of-conversion signal ( eoc ) pulses low when the first result becomes available, and for each subsequent result until the end of the conversion cycle. the end-of- last-conversion signal ( eolc ) goes low when the last conversion result is available (figures 5, 6, and 7). to start a conversion using external-clock mode, pull convst low for at least the acquisition time (t 1 ). the t/h acquires the signal while convst is low, and conversion begins on the rising edge of convst. apply an external clock to clk. to avoid t/h droop degrading the sampled analog input signals, the first clock pulse should occur within 10? from the rising edge of convst, and have a minimum clock frequency of 100khz. the first conversion result is available for read on the rising edge of the 17th clock cycle, and subsequent conversions after every third clock cycle thereafter (figures 5, 6, and 7). in both internal- and external-clock modes, convst must be held high until the last conversion result is read. for best operation, the rising edge of convst must be a clean, high-speed, low-jitter digital signal. table 3 shows the total throughput as a function of the clock frequency and the number of channels selected for conversion. the calculations use the nominal speed of the internal clock (10mhz) and a 200ns convst pulse width. table 2. configuration register bit/channel part no. state d0/ch0 d1/ch1 d2/ch2 d3/ch3 d4/ch4 d5/ch5 d6/ch6 d7/ch7 on11111111 max1316 max1320 max1324 off00000000 on1111nananana max1317 max1321 max1325 off0000nananana on 1 1 na na na na na na max1318 max1322 max1326 off 0 0 na na na na na na na = not applicable. figure 4. write timing d0?7 data-in rd cs wr t 2 t 5 t 6 t 14 t 15 t 7
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 17 data throughput the data throughput (f th ) of the max1316?ax1318/ max1320?ax1322/max1324?ax1326 is a function of the clock speed (f clk ). in internal-clock mode, f clk = 10mhz. in external-clock mode, 100khz f clk 12.5mhz. when reading during conversion (figures 5 and 6), calculate f th as follows: where n is the number of active channels and t quiet includes acquistion time t acq . t quiet is the period of bus inactivity before the rising edge of convst. typically use t quiet = t acq + 50ns, and prevent disturbance on the output bus from corrupting signal acquistion. see the starting a conversion section for more information. reading a conversion result reading during a conversion figures 5 and 6 show the interface signals for initiating a read operation during a conversion cycle. these figures show two channels selected for conversion. if more chan- nels are selected, the results are available successively every third clock cycle. cs can be low at all times; it can be low during the rd cycles, or it can be the same as rd . after initiating a conversion by bringing convst high, wait for eoc to go low (about 1.6? in internal-clock mode or 17 clock cycles in external-clock mode) before reading the first conversion result. read the conversion result by bringing rd low, thus latching the data to the parallel digital-output bus. bring rd high to release the digital bus. wait for the next falling edge of eoc (about 300ns in internal-clock mode or three clock cycles in external-clock mode) before reading the next result. when the last result is available, eolc goes low. f t xn f th quiet clk = + +?+ 1 16 3 1 1 () table 3. throughput vs. channels sampled (t quiet = t acq = 200ns, f clk = 10mhz) channels sampled (n) clock cycles until last result clock cycle for reading last conversion total conversion time (ns) samples per second (ksps) throughput per channel (ksps) 1 16 1 1900 526 526 2 19 1 2200 909 455 3 22 1 2500 1200 400 4 25 1 2800 1429 357 5 28 1 3100 1613 323 6 31 1 3400 1765 294 7 34 1 3700 1892 270 8 37 1 4000 2000 250 figure 5. read during conversion?wo channels selected, internal clock convst ch0 track hold d0?13 sample t 1 t 13 t 12 t 10 t 3 t 11 track ch1 t conv t next eoc rd t 20
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 18 ______________________________________________________________________________________ figure 6. read during conversion?wo channels selected, external clock convst clk ch0 track hold d0?13 sample t acq t 19 t 13 t 12 t quiet t 10 t 3 t 11 track ch1 eoc rd 1 2 3 16 17 18 19 20 21 22 23 1 t 16 t 17 t 18 figure 7. reading after conversion?ight channels selected, external clock clk d0?13 convst track hold sample t acq t 19 t 13 1 2 38 39 40 41 42 43 t 17 t 8 t 10 t 11 t 3 t 4 t 9 t 18 t 16 t 12 t quiet ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 only last pulse shown eoc rd cs eolc
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 19 reading after conversion figure 7 shows the interface signals for a read operation after a conversion with all eight channels enabled. at the falling edge of eolc , on the 38th clock pulse after the ini- tiation of a conversion, driving cs and rd low places the first conversion result onto the parallel bus, which can be latched on the rising edge of rd . successive low pulses of rd place the successive conversion results onto the bus. pulse convst low to initiate a new conversion. power-up reset at power-up, all channels are selected for conversion (see the configuration register section). after applying power, allow a 1.0ms wake-up time to elapse before ini- tiating the first conversion. then, hold convst high for at least 2.0? after the wake-up time is complete. if using an external clock, apply 20 clock pulses to clk with convst high before initiating the first conversion. reference internal reference the internal-reference circuits provide for analog input voltages of 0 to +5v unipolar (max1316/max1317/ max1318), ?v bipolar (max1320/max1321/max1322), or ?0v bipolar (max1324/max1325/max1326). install external capacitors for reference stability, as indicated in table 4, and as shown in the typical operating circuits . external reference connect a +2.0v to +3.0v external reference at ref ms and/or ref. when connecting an external reference, the input impedance is typically 5k ? . the external reference must be able to drive 200? of current and have a low output impedance. for more information about using external references see the transfer functions section. layout, grounding, and bypassing for best performance use pc boards with ground planes. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digital lines parallel to one another (especially clock lines), or do not run digital lines underneath the adc package. figure 8 shows the rec- ommended system ground connections when not using a ground plane. a single-point analog ground (star ground point) should be established at agnd, sepa- rate from the logic ground. all other analog grounds and dgnd should be connected to this ground. figure 8. power-supply grounding and bypassing table 4. reference bypass capacitors input voltage range location unipolar (f) bipolar (f) msv bypass capacitor to agnd 2.2 || 0.1 na ref ms bypass capacitor to agnd 0.01 0.01 (connect ref ms to ref) ref bypass capacitor to agnd 0.01 0.01 (connect ref ms to ref) ref+ bypass capacitor to agnd 0.1 0.1 ref+ to ref- capacitor 2.2 || 0.1 2.2 || 0.1 ref- bypass capacitor to agnd 0.1 0.1 com bypass capacitor to agnd 2.2 || 0.1 2.2 || 0.1 na = not applicable (connect msv directly to agnd). supplies av dd agnd dgnd v dd digital circuitry optional ferrite bead +5v return return +3v to +5v dv dd gnd max1316?ax1318 max1320?ax1322 max1324?ax1326
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 20 ______________________________________________________________________________________ no other digital system ground should be connected to this single-point analog ground. the ground return to the power supply for this ground should be low imped- ance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply may affect the high-speed comparator in the adc. bypass these supplies to the single-point analog ground with 0.1? and 2.2? bypass capacitors close to the device. if the +5v power supply is very noisy, a ferrite bead can be connected as a lowpass filter, as shown in figure 8. transfer functions bipolar ?0v devices table 5 and figure 9 show the two? complement trans- fer function for the max1324/max1325/max1326 with a ?0v input range. the full-scale input range (fsr) is eight times the voltage at ref. the internal +2.500v ref- erence gives a +20v fsr, while an external +2v to +3v reference allows an fsr of +16v to +24v, respectively. calculate the lsb size using the following equation: this equals 1.2207mv with a +2.5v internal reference. the input range is centered about v msv . normally, msv = agnd, and the input is symmetrical about zero. for a custom midscale voltage, drive msv with an external voltage source. noise present on msv directly couples into the adc result. use a precision, low-drift voltage reference with adequate bypassing to prevent msv from degrading adc performance. for maximum fsr, be careful not to violate the absolute maximum voltage ratings of the analog inputs when choosing v msv . determine the input voltage as a function of v ref , v msv , and the output code in decimal using the follow- ing equation: bipolar ?v devices table 6 and figure 10 show the two? complement transfer function for the max1320/max1321/max1322 with a ?v input range. the fsr is four times the volt- age at ref. the internal +2.500v reference gives a +10v fsr, while an external +2v to +3v reference allows an fsr of +8v to +12v, respectively. calculate the lsb size using the following equation: this equals 0.6104mv when using the internal reference. lsb v ref = 4 2 14 v lsb code v ch msv _ = + 10 lsb v ref = 8 2 14 figure 9. ?0v bipolar transfer function 8 x v ref 8 x v ref 8 x v ref 2 14 1 lsb = two's complement binary output code -8192 -8190 +8191 +8189 0x2000 0x2001 0x2002 0x2003 0x1fff 0x1ffe 0x1ffd 0x1ffc 0x3fff 0x0000 0x0001 -1 0 +1 (msv) input voltage (v ch_ - v msv in lsbs) table 5. ?0v bipolar code table two? complement binary output code decimal equivalent output (code 10 ) input voltage (v) (v ref = 2.5v, v msv = 0v) 01 1111 1111 1111 0x1fff 8191 9.9994 ?.5 lsb 01 1111 1111 1110 0x1ffe 8190 9.9982 ?.5 lsb 00 0000 0000 0001 0x0001 1 0.0018 ?.5 lsb 00 0000 0000 0000 0x0000 0 0.0006 ?.5 lsb 11 1111 1111 1111 0x3fff -1 -0.0006 ?.5 lsb 10 0000 0000 0001 0x2001 -8191 -9.9982 ?.5 lsb 10 0000 0000 0000 0x2000 -8192 -9.9994 ?.5 lsb
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 21 the input range is centered about v msv . normally, msv = agnd, and the input is symmetrical about zero. for a custom midscale voltage, drive msv with an external voltage source. noise present on msv directly couples into the adc result. use a precision, low-drift voltage reference with adequate bypassing to prevent msv from degrading adc performance. for maximum fsr, be careful not to violate the absolute maximum voltage ratings of the analog inputs when choosing v msv . determine the input voltage as a function of v ref , v msv , and the output code in decimal using the following equation: unipolar 0 to +5v devices table 7 and figure 11 show the offset binary transfer function for the max1316/max1317/max1318 with a 0 to +5v input range. the fsr is two times the voltage at ref. the internal +2.500v reference gives a +5v fsr, while an external +2v to +3v reference allows an fsr of +4v to +6v, respectively. calculate the lsb size using the following equation: this equals 0.3052mv when using the internal reference. lsb v ref = 2 2 14 v lsb code v ch msv _ = + 10 figure 10. ?v bipolar transfer function 4 x v ref 4 x v ref 4 x v ref 2 14 1 lsb = two's complement binary output code -8192 -8190 +8191 +8189 0x2000 0x2001 0x2002 0x2003 0x1fff 0x1ffe 0x1ffd 0x1ffc 0x3fff 0x0000 0x0001 -1 0 +1 (msv) input voltage (v ch_ - v msv in lsbs) table 6. ?v bipolar code table two? complement binary output code decimal equivalent output (code 10 ) input voltage (v) (v ref = 2.5v, v msv = 0v) 01 1111 1111 1111 0x1fff 8191 4.9997 ?.5 lsb 01 1111 1111 1110 0x1ffe 8190 4.9991 ?.5 lsb 00 0000 0000 0001 0x0001 1 0.0009 ?.5 lsb 00 0000 0000 0000 0x0000 0 0.0003 ?.5 lsb 11 1111 1111 1111 0x3fff -1 -0.0003 ?.5 lsb 10 0000 0000 0001 0x2001 -8191 -4.9991 ?.5 lsb 10 0000 0000 0000 0x2000 -8192 -4.9997 ?.5 lsb table 7. 0 to +5v unipolar code table binary output code decimal equivalent output (code 10 ) input voltage (v) (v ref = v refms = 2.5v) 11 1111 1111 1111 0x3fff 16383 4.9998 ?.5 lsb 11 1111 1111 1110 0x3ffe 16382 4.9995 ?.5 lsb 10 0000 0000 0001 0x2001 8193 2.5005 ?.5 lsb 10 0000 0000 0000 0x2000 8192 2.5002 ?.5 lsb 01 1111 1111 1111 0x1fff 8191 2.4998 ?.5 lsb 00 0000 0000 0001 0x0001 1 0.0005 ?.5 lsb 00 0000 0000 0000 0x0000 0 0.0002 ?.5 lsb
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 22 ______________________________________________________________________________________ the input range is centered about v msv , which is inter- nally set to +2.500v. for a custom midscale voltage, drive ref ms with an external voltage source and msv will follow ref ms . noise present on msv or ref ms directly couples into the adc result. use a precision, low-drift voltage reference with adequate bypassing to prevent msv from degrading adc performance. for maximum fsr, be careful not to violate the absolute maximum voltage ratings of the analog inputs when choosing v msv . determine the input voltage as a func- tion of v ref , v msv , and the output code in decimal using the following equation: definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. for these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. for these devices, the dnl of each digital output code is measured and the worst-case value is reported in the electrical characteristics table. a dnl error specifica- tion of less than ? lsb guarantees no missing codes and a monotonic transfer function. unipolar offset error for the unipolar max1316/max1317/max1318, the ideal zero-scale transition from 0x0000 to 0x0001 occurs at 1 lsb (see figure 11). the unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point. bipolar offset error for the bipolar max1320/max1321/max1322/ max1324/max1325/max1326, the ideal zero-point tran- sition from 0x3fff to 0x0000 occurs at msv, which is usually connected to ground (see figures 9 and 10). the bipolar offset error is the amount of deviation between the measured zero-point transition and the ideal zero-point transition. gain error the ideal full-scale transition from 0x1ffe to 0x1fff occurs at 1 lsb below full scale (see the transfer functions section). the gain error is the amount of devi- ation between the measured full-scale transition point and the ideal full-scale transition point, once offset error has been nullified. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full-scale analog input (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum analog-to-digital noise is caused by quantization noise error only and results directly from the adc? res- olution (n bits): where n = 14 bits. in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. snr n db =+ (. . ) 602 176 v lsb code v ch msv _ = + () 10 - 2.500v figure 11. 0 to +5v unipolar transfer function 2 x v ref 2 x v ref 2 x v ref 2 14 1 lsb = binary output code 0 2 16,383 16,381 0x0000 0x0001 0x0002 0x0003 0x3fff 0x3ffe 0x3ffd 0x3ffc 0x1fff 0x2000 0x2001 8190 8192 8194 (msv) input voltage (lsbs)
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 23 signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to the rms equivalent of all the other adc output signals: effective number of bits the effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the full- scale range of the adc, calculate the enob as follows: total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude and v 2 through v 5 are the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next-largest fre- quency component. aperture delay aperture delay (t ad ) is the time delay from the sampling clock edge to the instant when an actual sample is taken. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in aperture delay. channel-to-channel isolation channel-to-channel isolation indicates how well each analog input is isolated from the other channels. channel- to-channel isolation is measured by applying dc to chan- nels 1 to 7, while a -0.5dbfs sine wave is applied to channel 0. a 100khz fft is taken for channel 0 and channel 1. channel-to-channel isolation is expressed in db as the power ratio of the two 100khz magnitudes. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in a manner that ensures that the signal? slew rate does not limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3db. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as full- power input bandwidth frequency. chip information transistor count: 80,000 process: bicmos 0.6? thd vvvv v = +++ ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log enob sinad = -176 602 . . sinad db signal noise distortion rms rms ( ) log () = + ? ? ? ? ? ? 20
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 24 ______________________________________________________________________________________ typical operating circuits max1316 max1317 max1318 ch0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 av dd agnd dv dd dgnd msv ref ms ref ref+ com ref- +5v gnd +3v gnd d13 shdn allon analog inputs 0 to +5v parallel digital output convst clk digital interface and control 4 5 7 8 9 10 11 12 2, 3, 14, 16, 23 21 22 20 19 18 6 17 44 42 43 38 45 47 48 46 40 41 37 36 35 34 33 32 31 30 29 28 27 26 25 24 39 13 av dd av dd 15 1 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.01 f 0.1 f 0.01 f 2.2 f 2.2 f 2.2 f max1316 max1317 max1318 unipolar configuration intclk/extclk cs rd wr eoc eolc parallel digital i/o
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 25 typical operating circuits (continued) max1320 max1321 max1322 max1324 max1325 max1326 ch0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 av dd agnd dv dd dgnd msv ref ms ref ref+ com ref- +5v gnd +3v gnd d13 shdn allon bipolar analog inputs convst clk digital interface and control 4 5 7 8 9 10 11 12 2, 3, 14, 16, 23 21 22 20 19 18 6 17 44 42 43 38 45 47 48 46 40 41 37 36 35 34 33 32 31 30 29 28 27 26 25 24 39 13 av dd av dd 15 1 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.01 f 0.1 f 2.2 f 2.2 f max1322 max1324 max1320 max1325 max1321 max1326 bipolar configuration intclk/extclk cs rd wr eoc eolc parallel digital output parallel digital i/o
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 26 ______________________________________________________________________________________ pin configurations d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 av dd agnd agnd ch0 ch1 msv ch2 ch3 ch4 ch5 ch6 ch7 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 8-channel tqfp max1316 max1320 max1324 intclk/extclk agnd av dd agnd av dd ref ms ref ref+ com ref- agnd d0 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 allon shdn clk convst cs wr rd eolc eoc dgnd dv dd d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 av dd agnd agnd ch0 ch1 msv ch2 ch3 i.c. i.c. i.c. i.c. 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 4-channel tqfp max1317 max1321 max1325 intclk/extclk agnd av dd agnd av dd ref ms ref ref+ com ref- agnd d0 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 allon shdn clk convst cs wr rd eolc eoc dgnd dv dd d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 av dd agnd agnd ch0 ch1 msv i.c. i.c. i.c. i.c. i.c. i.c. 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 2-channel tqfp max1318 max1322 max1326 intclk/extclk agnd av dd agnd av dd ref ms ref ref+ com ref- agnd d0 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 allon shdn clk convst cs wr rd eolc eoc dgnd dv dd d13 top view
max1316?ax1318/max1320?ax1322/max1324?ax1326 8-/4-/2-channel, 14-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 27 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 32l/48l,tqfp.eps e 1 2 21-0054 package outline, 32/48l tqfp, 7x7x1.4mm e 2 2 21-0054 package outline, 32/48l tqfp, 7x7x1.4mm

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